As is known in the art, many electronics applications incorporate both silicon and column III-V circuits due to their unique performance characteristics. The silicon circuits are typically CMOS circuits used for digital signals and the column III-V circuits are for microwave, millimeterwave, and optical signals. Typically this integration is done by fabricating the silicon and column III-V circuits separately on different chips and then electrically connecting them, often with wire bonds. This process is expensive, limits integration complexity, increases the footprint, and introduces parasitic resistances and inductances which degrade circuit performance.
It is also known in the art that transistors have been formed on silicon having <100> and <111> crystallographic orientations (i.e., where, as is well known, a <100> crystallographic orientation is where the <100> axis of the crystalline silicon is normal (i.e., perpendicular) to the layer growing or depositing surface of the silicon and a <111> crystallographic orientation is where the <111> axis of the crystalline silicon is normal (i.e., perpendicular) to the layer growing or depositing surface of the silicon). Many years ago, CMOS was formed on silicon substrates having <111> crystallographic orientations; however this orientation is inferior for CMOS than the <100> crystallographic orientation due to a higher surface state density on <111> crystallographic orientation.
One CMOS structure is called a silicon-on-insulator (SOI) structure. This SOI structure includes a silicon substrate having a <100> crystallographic orientation. An insulating layer of SiO2 is formed on the silicon substrate. An upper device layer of silicon having a <100> crystallographic orientation is formed on the insulating layer; the insulating layer being used to assist electrical isolation of the CMOS transistor devices formed in the upper silicon layer. Thus, both the upper device layer and the substrate have the same crystallographic orientation (i.e., a <100> crystallographic orientation).
It is also known that it is desirable to have silicon CMOS transistors and column III-V (e.g. GaN, GaAs or InP) transistors on a common substrate. One structure used to form CMOS transistors and column III-V transistors on a common substrate is shown in FIG. 1. There, a GaAs transistor is formed on the same substrate as the CMOS transistors. It is also known that GaAs grown on a growth layer having a <100> crystallographic orientation provides a layer with a minimum number of crystalline defects. To provide this <100> growth layer for the GaAs device, a Ge layer having a <100> crystallographic orientation is used, as shown in FIG. 1 of the disclosure. However, Ge melts at 938 degrees C. and thereby limits the fabrication temperatures used in fabricating the CMOS devices. Also, Ge causes cross doping of the GaAs device resulting in increased microwave power loss. Additionally the starting wafer in FIG. 1 requires two layer transfers which is an expensive process.
It is also known in the art that a column III-V (such as a column III-N, for example, GaN, AlN, GaAlN, InGaN) device can be formed on a silicon substrate. Since it is preferable that the GaN device be formed with <111> crystallographic orientation to minimize crystal defects, the device is typically formed on a substrate (e.g., silicon) having a <111> crystallographic orientation. This device is shown in the middle portion of the structure shown in FIG. 2.
The inventors have recognized that there is an advantage in modifying the SOI structure described above by using a silicon substrate having a <111> crystallographic orientation rather than a <100> crystallographic orientation so that the column III-N device can be formed on the same <111> crystallographic orientation substrate as the CMOS devices with such substrate being crystallographically matched to the preferred <111> crystallographic orientation for the column III-N device. An additional advantage recognized by the inventors is having both the <111> silicon orientation and the <100> silicon orientation present in the starting wafer so that column III-As, column III-P and column III-Sb devices, which grow with fewest defects on the <100> orientation, can also be combined on the same substrate with column III-N devices and CMOS.
In one embodiment, a semiconductor structure is provided having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate.
In one embodiment, the column III-V transistor device is in contact with the substrate.
In one embodiment, the device is a column III-V device is a III-N device.
In one embodiment, the III-V device is a GaN, AlN, AlGaN or InGaN device.
In one embodiment, the crystallographic orientation of the substrate is <111> crystallographic orientation and wherein the crystallographic orientation of the silicon layer is <100> crystallographic orientation.
In one embodiment, CMOS transistors are disposed in the silicon layer.
In one embodiment, a semiconductor structure is provided having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and wherein the crystallographic orientation of the substrate is <111> and the crystallographic orientation of the silicon layer is <100>.
With such a structure:                1. The silicon substrate has the proper crystallographic orientation for GaN growth or other column III-N materials. For GaN power amplifiers it is attractive to minimize thermal resistance by having the GaN HEMT directly on the silicon surface with no intervening layers or wafer bonding interfaces. Furthermore selective etches (silicon and GaN are chemically dissimilar materials) can be used to fabricate thermal vias through the silicon substrate to the GaN HEMT.        2. There is no germanium in this structure so that normal CMOS thermal processing conditions can be used.        3. Germanium cross doping is eliminated.        4. The SOI wafers used in the embodiments described are relatively inexpensive due to high volume silicon production and that the SOI structure requires only one wafer bond compared with the structure shown in FIG. 1 which requires two wafer bonds.        5. Another benefit of the SOI wafer used in the embodiments described is that the top silicon layer has the proper crystallographic orientation for fabricating CMOS and metamorphic column III-V devices such as metamorphic column III-As, III-P, and III-Sb devices, therefore other metamorphic column III-V structures could be grown as well such as a metamorphic InP HBT, metamorphic HEMT (MHEMT) or metamorphic optical devices.        
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.